Memory devices and access methods

ABSTRACT

Apparatus, systems, and methods may operate to receive an external row address, receive a pipeline/burst select signal, select an external address path if the pipeline/burst signal indicates a pipeline mode of operation, and select an internal address path if the pipeline/burst signal indicates a burst mode of operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 08/650,719,filed May 20, 1996, which is a Continuation-In-Part of application Ser.No. 08/584,600, filed Jan. 1, 1996, now U.S. Pat. No. 5,966,724.

The below listed applications, as indicated by serial number and filingdate, are all assigned to the assignee of the instant application andwere or are co-pending with and related to the instant application: Ser.No. 08/370,761, filed Dec. 23, 1994 (now U.S. Pat. No. 5,526,320, issuedJun. 11, 1996); Ser. No. 08/386,894, filed Feb. 10, 1995 (now U.S. Pat.No. 5,610,864, issued Mar. 11, 1997); Ser. No. 08/386,563, filed Feb.10, 1995 (now U.S. Pat. No. 5,652,724, issued Jul. 29, 1997); Ser. No.08/457,650, filed Jun. 1, 1995 (now U.S. Pat. No. 6,804,760, issued Oct.12, 2004); Ser. No. 08/457,651, filed Jun. 1, 1995 (now U.S. Pat. No.5,675,549, issued Oct. 7, 1997); Ser. No. 08/497,354, filed Jun. 30,1995 (now U.S. Pat. No. 5,598,376, issued Jan. 28, 1997); Ser. No.08/505,576, filed Jul. 20, 1995 (now abandoned); Ser. No. 08/553,156,filed Nov. 7, 1995 (now U.S. Pat. No. 5,721,859, issued Feb. 24, 1998);Ser. No. 08/506,438, filed Jul. 24, 1995 (now U.S. Pat. No. 5,729,503,issued Mar. 17, 1998); and Ser. No. 08/630,279, filed Apr. 11, 1996 (nowU.S. Pat. No. 5,661,695, issued Aug. 26, 1997).

TECHNICAL FIELD

The embodiments disclosed relate to memory device architectures designedto provide high density data storage with high speed read and writeaccess cycles, including dynamic random access memory which isselectable between burst and pipelined modes.

BACKGROUND

Dynamic Random Access Memory devices (DRAMS) are among the highestvolume and most complex integrated circuits manufactured today. Exceptfor their high volume production, the state of the art manufacturingrequirements of these devices would cause them to be exorbitantlypriced. Yet, due to efficiencies associated with high volume production,the price per bit of these memory devices is continually declining. Thelow cost of memory has fueled the growth and development of the personalcomputer. As personal computers have become more advanced, they in turnhave required faster and more dense memory devices, but with the samelow cost of the standard DRAM. Fast page mode DRAMS are a popular DRAMtoday. In fast page mode operation, a row address strobe (/RAS) is usedto latch a row address portion of a multiplexed DRAM address. Multipleoccurrences of the column address strobe (/CAS) are then used to latchmultiple column addresses to access data within the selected row. On thefalling edge of /CAS an address is latched, and the DRAM outputs areenabled. When /CAS transitions high the DRAM outputs are placed in ahigh impedance state (tri-state). With advances in the production ofintegrated circuits, the internal circuitry of the DRAM operates fasterthan ever. This high speed circuitry has allowed for faster page modecycle times. A problem exists in the reading of a DRAM when the deviceis operated with minimum fast page mode cycle times. /CAS may be low foras little as 15 nanoseconds, and the data access time from /CAS to validoutput data (tCAC) may be up to 15 nanoseconds; therefore, in a worstcase scenario there is no time to latch the output data external to thememory device. For devices that operate faster than the specificationsrequire, the data may still only be valid for a few nanoseconds. On aheavily loaded microprocessor memory bus, trying to latch anasynchronous signal that is valid for only a few nanoseconds is verydifficult. Even providing a new address every 35 nanoseconds requireslarge address drivers which create significant amounts of electricalnoise within the system. To increase the data throughput of a memorysystem, it has been common practice to place multiple devices on acommon bus. For example, two fast page mode DRAMS may be connected tocommon address and data buses. One DRAM stores data for odd addresses,and the other for even addresses. The /CAS signal for the odd addressesis turned off (high) when the /CAS signal for the even addresses isturned on (low). This interleaved memory system provides data access attwice the rate of either device alone. If the first /CAS is low for 20nanoseconds and then high for 20 nanoseconds while the second /CAS goeslow, data can be accessed every 20 nanoseconds or 50 megahertz. If theaccess time from /CAS to data valid is fifteen nanoseconds, the datawill be valid for only five nanoseconds at the end of each 20 nanosecondperiod when both devices are operating in fast page mode. As cycle timesare shortened, the data valid period goes to zero.

There is a demand for faster, higher density, random access memoryintegrated circuits which provide a strategy for integration intotoday's personal computer systems. In an effort to meet this demand,numerous alternatives to the standard DRAM architecture have beenproposed. One method of providing a longer period of time when data isvalid at the outputs of a DRAM without increasing the fast page modecycle time is called Extended Data Out (EDO) mode. In an EDO DRAM thedata lines are not tri-stated between read cycles in a fast page modeoperation. Instead, data is held valid after /CAS goes high untilsometime after the next /CAS low pulse occurs, or until /RAS or theoutput enable (/OE) goes high. Determining when valid data will arriveat the outputs of a fast page mode or EDO DRAM can be a complex functionof when the column address inputs are valid, when /CAS falls, the stateof /OE and when /CAS rose in the previous cycle. The period during whichdata is valid with respect to the control line signals (especially /CAS)is determined by the specific implementation of the EDO mode, as adoptedby the various DRAM manufacturers.

Methods to shorten memory access cycles tend to require additionalcircuitry, additional control pins and nonstandard device pinouts. Theproposed industry standard synchronous DRAM (SDRAM)for example has anadditional pin for receiving a system clock signal. Since the systemclock is connected to each device in a memory system, it is highlyloaded, and it is always toggling circuitry in every device. SDRAMs alsohave a clock enable pin, a chip select pin and a data mask pin. Othersignals which appear to be similar in name to those found on standardDRAMs have dramatically different functionality on a SDRAM. The additionof several control pins has required a deviation in device pinout fromstandard DRAMs which further complicates design efforts to utilize thesenew devices. Significant amounts of additional circuitry are required inthe SDRAM devices which in turn result in higher device manufacturingcosts.

In order for existing computer systems to use an improved device havinga nonstandard pinout, those systems must be extensively modified.Additionally, existing computer system memory architectures are designedsuch that control and address signals may not be able to switch at thefrequencies required to operate the new memory device at high speed dueto large capacity loads on the signal lines. The Single In-Line MemoryModule (SIMM) provides an example of what has become an industrystandard form of packaging memory in a computer system. On a SIMM, alladdress lines connect to all DRAMs. Further, the row address strobe(/RAS) and the write enable (/WE) are often connected to each DRAM onthe SIMM. These lines may have high capacitive loads as a result of thenumber of device inputs driven by them. SIMM devices also typicallyground the output enable (/OE) pin making /OE a less attractivecandidate for providing extended functionality to the memory devices.

There is a great degree of resistance to any proposed deviations fromthe standard SIMM design due to the vast number of computers which useSIMMs. Industry's resistance to radical deviations from the standard,and the inability of current systems to accommodate the new memorydevices will delay their widespread acceptance. Therefore only limitedquantities of devices with radically different architectures will bemanufactured initially. This limited manufacture prevents the reductionin cost which typically can be accomplished through the manufacturingimprovements and efficiencies associated with a high volume product.

Additionally, there is a demand for multi-functional random accessmemory integrated circuits which provide a strategy for integration intosystems having differing memory needs. Some applications use randommemory access, while other applications use sequential memory access.However, prior asynchronous DRAMS did not have both burst and pipelinedmodes of operation. Thus, such prior asynchronous DRAMs did not supportapplications requiring both modes of operation. Consequently, the needarose for an asynchronous DRAM which had both burst and pipelined modesof operation.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the various embodiments of the invention, as well asadvantages, will be best understood by reference to the appended claims,detailed description of particular embodiments and accompanying drawingswhere:

FIG. 1 is an electrical schematic diagram of a memory device inaccordance with some embodiments of the invention;

FIG. 2 is a table showing linear versus interleaved addressing formats;

FIG. 3 is a pinout of the memory device of FIG. 1;

FIG. 4 is a timing diagram for a method of accessing the device of FIG.1;

FIG. 5 is a further timing diagram for accessing the device of FIG. 1;

FIG. 6 is an electrical schematic diagram of a Single In-Line MemoryModule in accordance with some embodiments of the invention;

FIG. 7 is a front view of a Single In-Line Memory Module designed inaccordance with the teachings of some embodiments of the invention;

FIG. 8 is a table of the pin numbers and signal names of the SingleIn-Line Memory Module of FIG. 7;

FIG. 9 is a block diagram of an embodiment of an exemplary memory devicein accordance with some embodiments of the invention;

FIG. 10 is a block diagram an embodiment of a portion of the memorydevice of FIG. 9;

FIG. 11 is a schematic diagram of a portion of control logic of thememory device of FIG. 9;

FIG. 12 is a process flow diagram for switching between burst andpipelined modes of operation in accordance with some embodiments of theinvention;

FIGS. 13 and 14 are timing diagrams for burst EDO write and read cycles,respectively, for a row-based switching embodiment in accordance withsome embodiments of the invention;

FIGS. 15 and 16 are timing diagrams for pipelined EDO write and readcycles, respectively, for the row-based switching embodiment of FIGS. 13and 14;

FIG. 17 is a timing diagram for a column-based switching embodiment inaccordance with some embodiments of the invention;

FIG. 18 is a top elevation view of a pinout diagram of an exemplaryDynamic Random Access Memory in accordance with some embodiments of theinvention;

FIG. 19 is a block diagram of an exemplary Single In-Line Memory Modulein accordance with some embodiments of the invention; and

FIG. 20 is a block diagram of an exemplary system in accordance withvarious embodiments of the invention.

DETAILED DESCRIPTION

FIG. 1 is a schematic representation of a sixteen megabit devicedesigned in accordance with some embodiments of the invention. Thedevice is organized as a 2Meg x 8 burst EDO DRAM having an eight bitdata input/output path 10 providing data storage for 2,097,152 bytes ofinformation in the memory array 12. The device of FIG. 1 has an industrystandard pinout for eight bit wide EDO DRAMs. An active-low row addressstrobe (/RAS) signal 14 is used to latch a first portion of amultiplexed memory address, from address inputs A0 through A10 16, inlatch 18. The latched row address 20 is decoded in row decoder 22. Thedecoded row address is used to select a row of the memory array 12. Acolumn address strobe (/CAS) signal 24 is used to latch a second portionof a memory address from address inputs 16 into column address counter26. The latched column address 28 is decoded in column address decoder30. The decoded column address is used to select a column of the memoryarray 12.

In a burst read cycle, data within the memory array located at the rowand column address selected by the row and column address decoders isread out of the memory array and sent along data path 32 to outputlatches 34. Data 10 driven from the burst EDO DRAM may be latchedexternal to the device in synchronization with /CAS after apredetermined number of /CAS cycle delays (latency). For a two cyclelatency design, the first /CAS falling edge is used to latch the initialaddress for the burst access. The first burst data from the memory isdriven from the memory after the second /CAS falling edge, and remainsvalid through the third /CAS falling edge. Once the memory device beginsto output data in a burst read cycle, the output drivers 34 willcontinue to drive the data lines without tri-stating the data outputsduring /CAS high intervals dependent on the state of the output enableand write enable (/OE and /WE) control lines, thus allowing additionaltime for the system to latch the output data. Once a row and a columnaddress are selected, additional transitions of the /CAS signal are usedto advance the column address within the column address counter in apredetermined sequence. The time at which data will be valid at theoutputs of the burst EDO DRAM is dependent only on the timing of the/CAS signal provided that /OE is maintained low, and /WE remains high.The output data signal levels may be driven in accordance with standardCMOS, TTL, LVTTL, GTL, HSTL, among other output level specifications.

The address may be advanced linearly, or in an interleaved fashion formaximum compatibility with the overall system requirements. FIG. 2 is atable which shows linear and interleaved addressing sequences for burstlengths of 2,4 and 8 cycles. The “V” for starting addresses A1 and A2 inthe table represent address values that remain unaltered through theburst sequence. The column address may be advanced with each /CAStransition, each pulse, or multiple of /CAS pulses in the event thatmore than one data word is read from the array with each column address.When the address is advanced with each transition of the /CAS signal,data is also driven from the part after each transition following thedevice latency which is then referenced to each edge of the /CAS signal.This allows for a burst access cycle where the highest switching controlline (/CAS) toggles only once (high to low or low to high) for eachmemory cycle. This is in contrast to standard DRAMs which require /CASto go low and then high for each cycle, and synchronous DRAMs whichrequire a full clock cycle (high and low transitions) for each memorycycle. For maximum compatibility with existing EDO DRAM devices, someembodiments will be further described in reference to a device designedto latch and advance a column address on falling edges of the /CASsignal.

It may be desirable to latch and increment the column address after thefirst /CAS falling edge in order to apply both the latched andincremented addresses to the array at the earliest opportunity in anaccess cycle. For example, a device may be designed to access two datawords per cycle (prefetch architecture). The memory array for a prefetcharchitecture device may be split into odd and even array halves. Thecolumn address least significant bit is then used to select between oddand even halves while the other column address bits select a columnwithin each of the array halves. In an interleaved access mode withcolumn address 1, data from columns 0 and 1 would be read and the datafrom column 1 would be output followed by the data from column 0 inaccordance with standard interleaved addressing as described in SDRAMspecifications. In a linear access mode column address 1 would beapplied to the odd array half, and incremented to address 2 foraccessing the even array half to fulfill the two word access. One methodof implementing this type of device architecture is to provide a columnaddress incrementing circuit between the column address counter and theeven array half. The incrementing circuit would increment the columnaddress only if the initial column address in a burst access cycle isodd, and the address mode is linear. Otherwise the incrementing circuitwould pass the column address unaltered. For a design using a prefetchof two data accesses per cycle, the column address would be advancedonce for every two active edges of the /CAS signal. Prefetcharchitectures where more than two data words are accessed are alsopossible.

Other memory architectures applicable to embodiments of the inventioninclude a pipelined architecture where memory accesses are performedsequentially, but each access may require more than a single cycle tocomplete. In a pipelined architecture the overall throughput of thememory will approach one access per cycle, but the data out of thememory may be offset by a number of cycles due to the pipeline lengthand/or the desired latency from /CAS.

In the burst access memory device, each new column address from thecolumn address counter is decoded and is used to access additional datawithin the memory array without the requirement of additional columnaddresses being specified on the address inputs 16. This burst sequenceof data will continue for each /CAS falling edge until a predeterminednumber of data accesses equal to the burst length has occurred. A /CASfalling edge received after the last burst address has been generatedwill latch another column address from the address inputs 16 and a newburst sequence will begin. Read data is latched and output with eachfalling edge of /CAS after the first /CAS latency.

For a burst write cycle, data 10 is latched in input data latches 34.Data targeted at the first address specified by the row and columnaddresses is latched with the /CAS signal when the first column addressis latched (write cycle data latency is zero). Other write cycle datalatency values are possible; however, for today's memory systems, zerois preferred. Additional input data words for storage at incrementedcolumn address locations are latched by /CAS on successive /CAS pulses.Input data from the input latches 34 is passed along data path 32 to thememory array where it is stored at the location selected by the row andcolumn address decoders. As in the burst read cycle previouslydescribed, a predetermined number of burst access writes will occurwithout the requirement of additional column addresses being provided onthe address lines 16. After the predetermined number of burst writes hasoccurred, a subsequent /CAS pulse will latch a new beginning columnaddress, and another burst read or write access will begin.

The memory device of FIG. 1 may include the option of switching betweenburst EDO and standard EDO modes of operation. In this case, the writeenable signal /WE 36 may be used at the row address latch time (/RASfalling, /CAS high) to determine whether memory accesses for that rowwill be burst or page mode cycles. If AVE is low when /RAS falls, burstaccess cycles are selected. If /WE is high at /RAS falling, standardextended data out (EDO) page mode cycles are selected. Both the burstand EDO page mode cycles allow for increased memory device operatingfrequencies by not requiring the data output drivers 34 to place thedata lines 10 in a high impedance state between data read cycles while/RAS is low. DRAM control circuitry 38, in addition to performingstandard DRAM control functions, controls the I/O circuitry 34 and thecolumn address counter/latch 26 in accordance with the mode selected by/WE when /RAS falls. In a burst mode only DRAM, or in a device designedwith an alternate method of switching between burst and non-burst accesscycles, the state of /WE when /RAS falls may be used to switch betweenother possible modes of operation such as interleaved versus linearaddressing modes.

The write enable signal is used in burst access cycles to select read orwrite burst accesses when the initial column address for a burst cycleis latched by /CAS. /WE low at the column address latch time selects aburst write access. /WE high at the column address latch time selects aburst read access. The level of the /WE signal must remain high for readand low for write burst accesses throughout the burst access. A low tohigh transition within a burst write access will terminate the burstaccess, preventing further writes from occurring. A high to lowtransition on /WE within a burst read access will likewise terminate theburst read access and will place the data output 10 in a high impedancestate. Transitions of the /WE signal may be locked out during criticaltiming periods within an access cycle in order to reduce the possibilityof triggering a false write cycle. After the critical timing period thestate of /WE will determine whether a burst access continues, isinitiated, or is terminated. Termination of a burst access resets theburst length counter and places the DRAM in a state to receive anotherburst access command. Both /RAS and /CAS going high during a burstaccess will also terminate the burst access cycle placing the datadrivers in a high impedance output state, and resetting the burst lengthcounter. Read data may remain valid at the device outputs if /RAS alonegoes high while /CAS is active for compatibility with hidden refreshcycles, otherwise /RAS high alone may be used to terminate a burstaccess. A minimum write enable pulse width is only required when it isdesired to terminate a burst read and then begin another burst read, orterminate a burst write prior to performing another burst write with aminimum delay between burst accesses. In the case of burst reads, /WEwill transition from high to low to terminate a first burst read, andthen JWE will transition back high prior to the next falling edge of/CAS in order to specify a new burst read cycle. For burst writes, /WEwould transition high to terminate a current burst write access, thenback low prior to the next falling edge of /CAS to initiate anotherburst write access.

A basic implementation of the device of FIG. 1 may include a fixed burstlength of 4, a fixed /CAS latency of 2 and a fixed interleaved sequenceof burst addresses. This basic implementation requires very littleadditional circuitry to the standard EDO page mode DRAM, and may be massproduced to provide the functions of both the standard EDO page mode andburst EDO DRAMs. This device also allows for the output enable pin (/OE)to be grounded for compatibility with many SIMM module designs. When notdisabled (tied to ground), /OE is an asynchronous control which willprevent data from being driven from the part in a read cycle if it isinactive (high) prior to /CAS falling and remains inactive beyond /CASrising. If these setup and hold conditions are not met, then the readdata may be driven for a portion of the read cycle. It is possible tosynchronize the /OE signal with /CAS, however this would typicallyincrease the /CAS to data valid delay time and does not allow for theread data to be disabled prior to /RAS high without an additional /CASlow pulse which would otherwise be unnecessary. In some embodiments, if/OE transitions high at any time during a read cycle the outputs willremain in a high impedance state until the next falling edge of /CASdespite further transitions of the /OE signal.

Programmability of the burst length, /CAS latency and address sequencesmay be accomplished through the use of a mode register 40 which latchesthe state of one or more of the address input signals 16 or data signals10 upon receipt of a write-/CAS-before-/RAS (WCBR) programming cycle. Insuch a device, outputs 44 from the mode register control the requiredcircuits on the DRAM. Burst length options of 2, 4, 8 and 20 full pageas well as /CAS latencies of 1, 2 and 3 may be provided. Other burstlength and latency options may be provided as the operating speeds ofthe device increase, and computer architectures evolve. The device ofFIG. 1 includes programmability of the address sequence by latching thestate of the least significant address bit during a WCBR cycle. Theburst length and /CAS latency for this particular embodiment are fixed.Other possible alterations in the feature sets of this DRAM includehaving a fixed burst mode only, selecting between standard fast pagemode (non-EDO) and burst mode, and using the output enable pin (/OE) 42in combination with /RAS to select between modes of operation. Also, aWCBR refresh cycle could be used to select the mode of operation ratherthan a control signal in combination with /RAS. A more complex memorydevice may provide additional modes of operation such as switchingbetween fast page mode, EDO page mode, static column mode and burstoperation through the use of various combinations of /WE and /OE at /RASfalling time. One mode from a similar set of modes may be selectedthrough the use of a WCBR cycle using multiple address or data lines toencode the desired mode. Alternately, a device with multiple modes ofoperation may have wire bond locations, or programmable fuses which maybe used to program the mode of operation of the device.

A sixteen bit wide burst EDO mode DRAM designed in accordance with theteachings of some embodiments of this invention has two column addressstrobe input pins /CASH and /CASL. For read cycles only /CASL needs totoggle. /CASH is may be high or may toggle with /CASL during burst readcycles, all sixteen data bits will be driven out of part during a readcycle even if /CASH remains inactive. In a typical system application, amicroprocessor will read all data bits on a data bus in each read cycle,but may only write certain bytes of data in a write cycle. Allowing oneof the /CAS control signals to remain static during read cycles helps toreduce overall power consumption and noise within the system. For burstwrite access cycles, each of the /CAS signals (CASH and /CASL) acts as awrite enable for an eight bit width of the data. All sixteen data inputswill be latched when the first of the /CAS signals transitions low. Ifonly one /CAS signal transitions low, then the eight bits of dataassociated with the /CAS that remained high will not be stored in thememory.

Just as fast page mode DRAMs and EDO DRAMs are available in numerousconfigurations including x1, x4, x8 and x16 data widths, and 1 Megabit,4 Megabit, 16 Megabit and 64 Megabit densities; the memory device ofsome embodiments of the invention may take the form of many differentmemory organizations. It is believed that one who is skilled in the artof integrated circuit memory design can, with the aide of thisspecification design a variety of memory devices which do not departfrom the scope of the various embodiments. It is therefore believed thatdetailed descriptions of the various memory device organizationsapplicable to the embodiments are not necessary.

FIG. 3 shows a preferred pinout for the device of FIG. 1. It should benoted that the pinout for this new burst EDO memory device is identicalto the pinout for a standard EDO DRAM. The common pinout allows this newdevice to be used in existing memory designs with minimum designchanges. The common pinout also allows for ease of new designs by thoseof skill in the art who are familiar with the standard EDO DRAM pinout.Variations of the described embodiments which maintain the standard EDODRAM pinout include driving the /CAS pin with a system clock signal tosynchronize data access of the memory device with the system clock. Forthis embodiment, it may be desirable to use the first /CAS active edgeafter /RAS falls to latch the row address, a later edge may be used tolatch the first column address of a burst access cycle. After row andcolumn addresses are latched within the device, the address may beincremented internally to provide burst access cycles in synchronizationwith the system clock. Other pin function alternatives include drivingthe burst address incrementing signal on the /OE pin since the part doesnot require a data output disable function on this pin. Other alternateuses of the /OE pin also allow the device to maintain the standard EDOpinout, but provide increased functionality such as burst mode access.The /OE pin may be used to signal the presence of a valid columnstarting address, or to terminate a burst access. Each of theseembodiments provides for a high speed burst access memory device whichmay be used in current memory systems with a minimum amount of redesign.

FIG. 4 is a timing diagram for performing a burst read followed by aburst write of the device of FIG. 1. In FIG. 4, a row address is latchedby the /RAS signal. AWE is low when /RAS falls for an embodiment of thedesign where the state of the /WE pin is used to specify a burst accesscycle at /RAS time. Next, /CAS is driven low with /WE high to initiate aburst read access, and the column address is latched. The data outsignals (DQ's) are not driven in the first /CAS cycle. On the secondfalling edge of the /CAS signal, the internal address generationcircuitry advances the column address and begins another access of thearray, and the first data out is driven from the device after a /CAS todata access time (tCAC). Additional burst access cycles continue, for adevice with a specified burst length of four, until the fifth fallingedge of /CAS which latches a new column address for a new burst readaccess. /WE falling in the fifth /CAS cycle terminates the burst access,and initializes the device for additional burst accesses. The sixthfalling edge of /CAS with /WE low is used to latch a new burst address,latch input data and begin a burst write access of the device.Additional data values are latched on successive /CAS falling edgesuntil /RAS rises to terminate the burst access.

FIG. 5 is a timing diagram depicting burst write access cycles followedby burst read cycles. As in FIG. 4, the /RAS signal is used to latch therow address. The first /CAS falling edge in combination with /WE lowbegins a burst write access with the first data being latched.Additional data values are latched with successive /CAS falling edges,and the memory address is advanced internal to the device in either aninterleaved or sequential manner. On the fifth /CAS falling edge a newcolumn address and associated write data are latched. The burst writeaccess cycles continue until the /WE signal goes high in the sixth /CAScycle. The transition of the /WE signal terminates the burst writeaccess. The seventh /CAS low transition latches a new column address andbegins a burst read access ([WE is high). The burst read continues until/RAS rises terminating the burst cycles.

It should be noted from FIGS. 3 and 4 that for burst read cycles thedata remains valid on the device outputs as long as the /OE pin is low,except for brief periods of data transition. Also, since the /WE pin islow prior to or when /CAS falls, the data input/output lines are notdriven from the part during write cycles, and the /OE pin is a “don'tcare”. Only the /CAS signal and the data signals toggle at relativelyhigh frequency, and no control signals other than /CAS are required tobe in an active or inactive state for one /CAS cycle time or less. Thisis in contrast to SDRAMs which often require row address strobes, columnaddress strobes, data mask, and read/write control signals to be validfor one clock cycle or less for various device functions. Typical DRAMsalso allow for the column address to propagate through to the array tobegin a data access prior to /CAS falling. This is done to provide fastdata access from /CAS falling if the address has been valid for asufficient period of time prior to /CAS falling for the data to havebeen accessed from the array. In these designs an address transitiondetection circuit is used to restart the memory access if the columnaddress changes prior to /CAS falling. This method actually requiresadditional time for performing a memory access since it must allow for aperiod of time at the beginning of each memory cycle after the lastaddress transition to prepare for a new column address. Changes in thecolumn address just prior to /CAS falling may increase the access timeby approximately five nanoseconds. An embodiment of the invention willnot allow the column address to propagate through to the array untilafter /CAS has fallen. This eliminates the need for address transitiondetection circuitry, and allows for a fixed array access relative to/CAS. However, it should be understood that the address counter may beadvanced early on /CAS in accordance with some embodiments of theinvention.

FIG. 6 is a schematic representation of a single in-line memory module(SIMM) designed in accordance with some embodiments of the invention.The SIMM has a standard SIMM module pinout for physical compatibilitywith existing systems and sockets. Functional compatibility with EDOpage mode SIMMs is maintained when each of the 2 Meg×8 memory devices10, 12, 14 and 16 are operated in an EDO page mode. Each of the /CASsignals 18, 20, 22 and 24 control one byte width of the 32 bit data bus26, 28, 30 and 32. A /RAS 34 signal is used to latch a row address ineach of the memory devices, and is used in combination with [WE 36 toselect between page mode and burst mode access cycles. Address signals38 provide a multiplexed row and column address to each memory device onthe SIMM. In burst mode, only active /CAS control lines are required totoggle at the operating frequency of the device, or at half thefrequency if each edge of the /CAS signal is used as described above.The data lines are required to be switchable at half of the frequency ofthe /CAS lines or at the same frequency, and the other control andaddress signals switch at lower frequencies than /CAS and the datalines. As shown in FIG. 6, each /CAS signal and each data line isconnected to a single memory device allowing for higher frequencyswitching than the other control and address signals. Each of the memorydevices 10, 12, 14 and 16 is designed in accordance with embodiments ofthe invention allowing for a burst mode of operation providing internaladdress generation for sequential or interleaved data access frommultiple memory address locations with timing relative to the /CAScontrol lines after a first row and column address are latched.

FIG. 7 shows a front view of another SIMM designed in accordance withsome embodiments of the invention. Each device on the SIMM is a 4Megabit DRAM organized as 1 Meg×4. In this configuration, a single /CAScontrols two memory devices to provide access to a byte width of thedata bus. The eight devices shown form a 4 Megabyte SIMM in a 32 bitwidth. For an 8 Megabyte SIMM in a 32 bit width, there are eightadditional devices on the back side (not shown).

FIG. 8 shows a preferred pinout for a memory module designed inaccordance with the device of FIG. 7. This pinout is compatible withpinouts for Fast Page Mode SIMMs and EDO SIMMs. A presence detect pin isprovided for indication of EDO operation on pin 66, and in accordancewith standard EDO part types, an /OE input is provided on pin 46.

Alternate embodiments of the SIMM modules of FIG.'s 5, 6, and 7 includethe use of two /RAS signals with each controlling a sixteen bit width ofthe data bus in accordance with standard SIMM module pinouts. Four more2M×8 EDO Burst Mode DRAMs may be added to the device of FIG. 6 toprovide for a 4M×32 bit SIMM. Sixteen bit wide DRAMs may also be used,these will typically have two /CAS signals each of which controls aneight bit data width. The incorporation of parity bits, or errordetection and correction circuitry provide other possible SIMM moduleconfigurations. Methods of performing error detection and/or correctionare well known to those of skill in the art, and detailed descriptionsof such circuits are not provided in this application. Additional SIMMdesigns using the novel memory device described herein may be designedby one of skill in the art with the aid of this specification. Theembodiments have been described with reference to SIMM designs, but isnot limited to SIMMs. Embodiments of the invention are equallyapplicable to other types of memory modules including Dual In-LineMemory Modules (DIMMs) and Multi-Chip Modules (MCMs).

Burst/Pipelined Mode Embodiment

Referring to FIG. 9, there is shown a block diagram of a memory device(memory) 100 in accordance with various embodiments. Memory 100 in theembodiment illustrative shown is an asynchronous DRAM. By asynchronousit should be understood that operation of memory 100 need not besynchronized to an external clock signal. In other words, no systemclock signal need be applied to memory 100. Consequently, memory 100 issmaller, and requires less circuitry and control pins than an SDRAM.

Memory 100 receives several signals, including /RAS and /CAS signals112, 114, /WE signal 117, address (ADDR) signal 115, and /OE signal 118.ADDR signal 115 may be made up of input pins (inputs) A0 through Aninclusive (A0-An), where n is an integer greater than zero.Multiplexer/Column-Address Buffer 122 is coupled for receiving ADDRsignal 115. Furthermore, in accordance with one embodiment of theinvention, an input control signal is provided to memory 100. Thissignal is pipelined EDO/burst EDO select (P/B) signal 120, where the “/”indicates that burst mode is active low. P/B signal 120 may be suppliedexternally to memory 100 (e.g., via a control pin of memory 100) tocontrol logic 121. Alternatively, P/B signal 120 may be omitted for astandard enable signal to generate mode select internal to control logic121.

Memory 100 includes memory array 111. While memory array 111 is referredto in the singular, it should be understood, as illustratively shown inFIG. 9, that memory array 111 may be made up of one or more addressablememory arrays. Memory 100 may provide an output read from memory array111 via data (DQ) signal 116. Alternatively, memory 100 is capable ofreceiving information to be stored in memory array 111 via DQ signal116. DQ signal 116 is made up of I/O pins DQ1 through DQm inclusive(DQ1-DQm), where m represents an integer greater than or equal to one.Alternatively, separate data input and output paths may be used.

Memory 100 also includes many known elements such as row address buffers101, refresh counter 102, refresh controller 103, column decoder 104,data-in buffer 105, data-out buffer 107, I/O gating sense amplifiers106, row decoder 108, and timing control 109.

Referring to FIG. 10, there is shown a block diagram of an embodiment ofa portion of memory 100 of FIG. 9. ADDR signal 115 provides externalinputs XA0-XAn. Inputs XA2-XAn are provided directly to temporarystorage 119. Temporary storage 119 may be a latch or other memorydevice. Input XA1 is provided to multiplexer (MUX) 124, and input XA0 isprovided to MUX 125. After which inputs XA1 and XA0 are provided torespective locations in temporary storage 119.

MUXs 124,125 also receive newburst signal 110 from control logic 121(shown in FIG. 9). Newburst signal 110 is employed as a select signal asapplied to MUXs 124, 125. Thus, if newburst signal 110 is active, memory100 is in burst mode. Consequently, count 0 and count 1 signals 140, 141are selected over XA0 and XA1 signals as applied to MUXs 124, 125. Ifnewburst signal 110 is not active, memory 100 is in pipelined mode. As aresult, XA0 and XA1 are selected over signals 140, 141 as applied toMUXs 124, 125.

In burst mode, newburst signal 110 is used to control counter 149 toload and increment values. Counter 149 loads address XA0 and XA1. Aftera first /CAS signal 114 cycle in burst mode which uses the initialexternal values supplied for addresses XA0 and XA1, counter 149increments those initial values and provides new internally generatedaddresses A0 and A1 by supplying count 0 signal 140 and count I signal141 to respective A0 and A1 locations in temporary storage 119 throughMUXs 125, 124. In this manner, internal addresses may be generated basedon an initial external address.

While counter 149 is shown as a two (2) bit counter, it will be readilyapparent to one with ordinary skill in the art that this is merelyrepresentative of one embodiment of the invention. Consequently, itshould be understood that other counter sizes may be employed inaccordance with various embodiments. Moreover, counter 149 may alsoinclude burst length counter 143. In such a case, burst length counter143 may include a latch for temporarily storing a current burst lengthcount and a comparator for ensuring the count does not exceed a maximumlength for a burst sequence.

Referring now to FIG. 11, there is shown a schematic diagram of modecircuitry 138 for generating newburst signal 110 in accordance withvarious embodiments. Mode circuitry 138 is a portion of control logic121 (shown in FIG. 9). As shown, either /OE signal 118, /WE signal 117,or P/B signal 120 maybe used to provide newburst signal 110. CYa and CYbsignals 126, 127 are provided by burst length counter 143 (shown in FIG.10). Newburst signal 110 is employed to reset CYa and CYb signals 126,127 (for example to binary (1, 1)). Signals 126, 127 are decrementedbinarily (for example, (1, 1), (1, 0), (0, 1), (0, 0)) such that when anend of a burst length is reached (for example, (0, 0) for a 4-bit burstlength), newburst signal 110 is enabled.

/CAS signal 114 is provided to delays 128, 129. In this embodiment,delay 128 is longer than that of delay 129.

Flip-flop 130 is made up of two NAND gates 131, 132. Output from delay129 is used to reset and enable flip-flop 130.

In the case where burst mode is selected (active low), mode select (/MS)signal 142 will be low. /MS signal 142 may be any of signals 117, 118,120 or a combination thereof. As /MS signal 142 is low, its input to NORgates 113, 136 will be low (“logic zero”). Flip-flop 130 will be setsuch that output from it to NOR gate 136 is also low provided thatoutput from delay 129 is low and that output from NOR gate 135 is low.Output from NOR gate 135 will go high when /CAS signal 114 rises causinga low pulse out of NAND gate 134, and CYa 126 and CYb 127 are both lowindicating that the current burst sequence is complete. Both CYb 127 andCYa 126 are set high at the beginning of a burst sequence. Consequently,newburst signal 110 will remain low until burst mode is interrupted orcompleted.

If pipelined mode is selected, /MS signal 142 will be high. Thus, inputsto NOR gate 136 will be high (“logic one”), and thus newburst signal 110will remain high until pipelined mode is interrupted.

With renewed reference to FIGS. 9 and 10, the following two examples ofoperation of memory 100 should be considered.

1. If mode select is active high (e.g., logic “1 ”), pipelined EDO modeis selected for operation of memory 100. Control logic 121 in responseto receiving mode select pipelined information, provides newburst signal110 to MUX 123 to select external input XA0-XAn. In this manner anexternal address via ADDR signal 115 may be sent through buffer 122 todecoder 104 for each /CAS signal 114 cycle for pipelined EDO mode. Inother words, a new external column address for memory array 111 may beprovided for each access to memory 100. Thus, while memory 100 is inpipelined EDO mode, newburst signal 110 instructs buffer 122 to selectaddress input only from ADDR signal 115.

2. Alternatively, if mode select is active low (e.g., logic “0”), burstEDO mode is selected for operation of memory 100. Control logic 121 inresponse to receiving mode select burst information, provides newburstsignal 110 to select input from buffer 122 via temporary storage 119 andcounter 149. In this manner, for an access to memory 100, an addresssent from buffer 122 to decoder 104 is selected, namely the currentexternal address stored in buffer 122. This address is then incrementedin accordance with burst EDO mode by operation of counter 149 andprovided to decoder 104 through buffer 122.

It should be readily appreciated that embodiments of the inventionprovide switching between burst and pipelined EDO modes of operation ofmemory 100 for page mode accessing in either mode.

When accessing several different column locations in a row of memoryarray 111 (page mode access), a new external column address for eachaccess to memory array 1 1 1 may be provided to memory 100 for pipelinedEDO mode of operation. Thus, successive external addresses, one for each/CAS signal 114 cycle, may be provided to memory 100. This isparticularly useful in applications when column accesses are in a randomor a patternless-series of column addresses. By patternless-series, itshould be understood to mean a manner of memory addressing which doesnot have to comport with any predefined scheme.

When accessing several different column locations in a row of memoryarray 111 (again, page mode access), after receipt of an externaladdress for access to memory array 111, a subsequent, new internalcolumn addresses may be generated by memory 100 for each subsequentaccess to memory array 111 in burst EDO mode of operation. This isparticularly useful in applications when column accesses are in apredefined-series or in a sequence. Such predefined-series andsequential operation include interleaved and linear memory addressingschemes. It should be further understood that successive externaladdresses, one for each set of /CAS signal 114 cycles, may be providedto memory 100 in accordance with various embodiments for continuedbursting.

With continued reference to FIG. 9 and reference to FIG. 12, which is aprocess flow diagram for switching between burst and pipelined EDO modesof operation in accordance with various embodiments, one type ofswitching operation for memory 100 is explained. At step 153, memory 100is initialized. After which, it is determined whether a row address hasbeen received at step 154. If a row address has not been received,memory 100 stays in wait mode until a row address is received.

If a row address has been received, at step 159 it is determined whetherburst or pipelined EDO mode is desired. If pipelined EDO mode isdesired, an external address path is selected at step 158. By path orpathway it should be understood to include one or more signals. At step150, memory 100 is instructed whether to read (output) or write (input)information. If memory 100 is to read information., an external columnaddress is obtained at step 151. Next, at step 152, information isobtained from memory array 111 corresponding to the row address receivedat step 154 and the external column address obtained at step 151. Atstep 153, it is determined whether information should continue to beread from memory 100 in the current pipelined EDO mode. If yes, anotherexternal column address is obtained at step 151 ; however, if no, memory153 must wait for a next instruction.

If at step 150, memory 100 was instructed to write information, then anexternal column address is obtained at step 155. After which, theappropriate information is provided to memory array 111 at step 156 at alocation corresponding to the row address received at step 154 and theexternal column address obtained at step 155. At step 157, it isdetermined whether memory 100 is to continue writing information in thecurrent pipelined EDO mode. If yes, then another external column addressis obtained at step 155. If no, memory 100 waits for a next instructionat step 174.

If at step 159, it was determined that memory 100 should be in burst EDOmode, then an initial stored external address path is selected at step160. At step 161 it is determined whether information is to be read orwritten to memory 100. If information is to be read from memory 100,then at step 162 an initial external column address is obtained. At step163 information is obtained from memory array 111 at the locationspecified by the row address received at step 154 and the externalcolumn address obtained at step 162.

At step 164, an internal column address is generated for burst EDO modeand an alternative address path for providing internal addresses totemporary storage 119 (shown in FIG. 10) is selected. At step 165,information is obtained from memory array 111 according to the rowaddress specified at step 154 and the internal column address specifiedat step 164.

At step 166 it is determined whether to continue generating internalcolumn addresses. If yes, at step 164 the next internal column addressin the predefined-series is generated. If no, it is determined whetherinformation is to be read from memory 100 in the current mode at step167. If information is to continue to be read, then another externalcolumn address is obtained at step 162. If no, memory 100 waits for anext instruction at step 174.

If at step 161 memory 100 is instructed to write information to memoryarray 111, then at step 168 an initial external column address isobtained. Next, at step 169, information is provided to memory array 111at the location specified by the row address received at step 154 andthe external column address obtained at step 168.

At step 170, an internal column address is generated in accordance witha predefined-series. At step 171, information is provided to memoryarray 111 at the location specified by the row address received at step154 and the internal column address generated at step 170.

At step 172 it is determined whether to continue generating internalcolumn addresses. If internal column addresses are to be continued to begenerated, then the next internal column address in thepredefined-series is generated at step 170. If no, then at step 173 itis determined whether information is to continue to be written to memory100 in the burst EDO mode. If yes, then another initial external columnaddress is obtained at step 168. If no, memory 100 waits for a nextinstruction at step 174.

Embodiments of the invention facilitate random/patternless-series columnaccessing (using externally generated addresses exclusively) andpredefined-series/sequential column accessing (using an initialexternally generated address followed by one or more internallygenerated addresses). This is done without the additionalabove-described undesirable features associated with SDRAMs. The variousembodiments provide switching between burst access, and non-burst accessor pipelined modes of operation without ceasing (“on-the-fly”). No WCBRcycle is needed with burst/pipelined mode switching during operation.Thus, the ability to increase speed and operating performance isfacilitated.

Furthermore, owing to the ability to provide both burst and pipelinedEDO modes of operation for memory 100, this disclosure facilitates manyadditional embodiments, some of which are described below.

Referring now to FIG. 13, there is shown a timing diagram illustrativeof burst EDO write cycles for a row-based switching embodiment inaccordance with various embodiments. For row-based switching, either /OEsignal 118 or /WE signal 117 may be used for mode select. For example,either /OE signal 118 or /WE signal 117 may be provided to modecircuitry 138 (shown in FIG. 11). Mode circuitry 138 (shown in FIG. 11)may be set by either /OE signal 118 or /WE signal 117 when /RAS signal112 is active. Thus, any need for an external mode select control signalis eliminated. Mode circuitry 138 (shown in FIG. 11) may be set for theduration of a current row access (page mode access), and /OE signal 118and /WE signal 117 retain their functionality for one or more columnaccesses on the current row. /RAS signal 112 transitions to active lowat time 175. At which time, /OE signal 118 is active low for selectingburst EDO mode, and /OE signal 118 is a “don't care” condition for theremainder of /RAS signal 112 for the current write cycles. (e.g., /CAScycles 180 through 183, inclusive).

At time 175, ADDR signal 115 has provided row address 176. Row address176 indicates which row in memory array 111 (shown in FIG. 9) is to beaccessed. Thus, row address 176 is latched by transition of /RAS signal112 from high to low at time 175.

At time 177, /CAS signal 114 transitions to active low. At which time,/WE signal 117 is active low. Consequently, memory 100 (shown in FIG. 9)is instructed to write information to memory array 111 (also shown inFIG. 9). Also, at time 177, ADDR signal 115 provides an initial externalcolumn address (COL b) 178. Address 178 indicates a location on row 176in which writing of information is to begin. Accordingly, data (DIN b)179 from DQ signal 116 is input to memory 100 (shown in FIG. 9).

Column address 178 is advanced on subsequent /CAS signal 114 cycles 181through 183, inclusive (181-183). Accordingly, data (DIN b+1, DIN b+2,and DIN b+3) 184 through 186, inclusive, is stored on each cycle181-183, respectively.

After the fourth memory access, a new external address 187 is appliedvia ADDR signal 115 for further inputting of information to memory 100(shown in FIG. 9) without any /CAS cycle latency.

Referring to FIG. 14, there is shown a timing diagram illustrative ofburst EDO read cycles for a row-based switching embodiment in accordancewith various embodiments. /RAS signal 112 transitions to active low attime 190. At which time, /OE signal 118 is active low for selectingburst EDO mode, and ADDR signal 115 has provided row address 191, namelya row in memory array 111 (shown in FIG. 9) to be accessed. Row address191 is latched by transition of /RAS signal 112 from high to low at time190.

At time 192, /CAS signal 114 transitions to active low, latching columnaddress (COL b) 193. Address 193 is an externally generated addressprovided to memory 100 (shown in FIG. 9) via ADDR signal 115. As [WEsignal 117 is high (inactive) at time 192, memory 100 (shown in FIG. 9)is instructed to read information from memory array 111 (also shown inFIG. 9). After /CAS cycle 194, an additional /CAS cycle takes place,namely /CAS cycle 195, for a two /CAS signal 114 cycle latency (cycles194 and 195). Notably, for continued, successive bursting, only theinitial two /CAS cycle latency is incurred.

By time 200, the beginning of the third /CAS cycle (/CAS cycle 196),data (DOUT b) 201 from row 191, column 193 is valid. DOUTh is outputteda tCAC (access time from /CAS) from the beginning of the second CAScycle 195, and is outputted along DQ signal 116. After cycle 194, oneach following /CAS cycle 195 through 197, inclusive, an internaladdress is generated for outputting data (DOUT b+1, b+2, and b+3) 202,203, and 204, respectively, on DQ signal 116. Meanwhile at time 205, anew external column address 206 is latched by transition of /CAS signal114 from high to low.

Referring to FIG. 15, there is shown a timing diagram illustrative ofpipelined EDO write cycles for a row-based switching embodiment inaccordance with various embodiments. /RAS signal 112 transitions toactive low at time 210, latching row address 211. As /OE signal 118 ishigh at time 210, pipelined mode is selected. As /WE signal 117 is lowat time 216, memory 100 (shown in FIG. 9) is instructed to writeinformation to memory array 111 (shown in FIG. 9).

At time 216, /CAS 114 transitions from high to low to begin /CAS cycle 212. This transition causes row address 211 and external column address(COL b) 2 17 to be accessed for writing data (DIN b) 221 from DQ signal116 to memory array 111 (shown in FIG. 9). On the next and following/CAS cycles (e.g., /CAS cycles 213, 214, 215, a random or patternlessseries of external column addresses (e.g., external column addresses218, 219, 220) may be received for writing data (e.g., DIN e, w, y) fromDQ signal 116 to memory 100 (shown in FIG. 9). Receiving of externaladdresses may continue thereafter without any /CAS cycle latency.

Referring now to FIG. 16, there is shown a timing diagram illustrativeof pipelined EDO read cycles for a row-based switching embodiment inaccordance with various embodiments. At time 225, /RAS signal 112transitions to active low, and row address 226 is latched from ADDRsignal 115. Also, at time 225, /OE signal 118 is high, and thuspipelined mode is selected. At time 227, /WE signal 117 is high, andthus memory 100 (shown in FIG. 9) is instructed to read from memoryarray 111 (also shown in FIG. 9).

At time 227, /CAS signal 114 begins cycling, and consequently externalcolumn address (COL b) 234 may be provided to MUX 123 (shown in FIG. 9).Moreover, a new external column address (e.g., COL e, w, y, n, d, m) maybe provided to MUX 123 (shown in FIG. 9) on each subsequent /CAS cycle229 through 233, inclusive. However, there is a two /CAS cycle latency,namely /CAS cycles 228, 229, from time 227 when external column address234 is received and reading or outputting data (DOUT b) 235 associatedwith address 234 onto signal DQ 116.

While this row-based switching embodiment has been illustratively shownhaving four /CAS cycles prior to initiation of receipt of a new externaladdress while in burst EDO mode, it will be appreciated by those ofordinary skill in the art that fewer or more /CAS cycles may be used.Furthermore, while data out was incrementally increased (i.e., b, b+1,etc.) for purposes of illustration of burst EDO write and readoperations, it will be appreciated by those of ordinary skill in the artthat an interleaved or another patterned, internally generatedaddressing scheme may be employed. Also, AWE signal 117 was not used formode selection in this example; however, it will be readily appreciatedto those of ordinary skill in the art that AWE signal 117 may be usedinstead of /OE signal 118 for mode selection.

As mentioned above, embodiments of the invention facilitate manyapplications in addition to row-based switching. By way of example andnot limitation, some other possible embodiments are described herein.

In column-based switching, switching between burst EDO and pipelined EDOmodes is accomplished on successive /CAS cycles. Moreover, this type ofswitching may be accomplished on either read or write cycles, e.g., froma burst EDO read cycle to a pipelined EDO read cycle and vice-versa, orfrom a burst EDO write cycle to a pipelined EDO write cycle andvice-versa.

For this embodiment, /OE signal 118 functionality must be changed, as itis used to disable output drivers, to be used as an input for modeselection (i.e., a signal equivalent to P/B 120). For example, referringto FIG. 17, there is shown a timing diagram for column-base switching inaccordance with various embodiments. When /OE signal 118 is low, memory100 (shown in FIG. 9) operates in burst mode 258, and when /OE signal118 is high, memory 100 (shown in FIG. 9) operates in pipelined mode259.

In application-based switching, a WCBR (write /CAS before /RAS) programcycle following a memory 100 (shown in FIG. 9) initialization routinemay be applied to mode circuitry 138 (shown in FIG. 1) to select adesired EDO mode. In such a case, memory 100 (shown in FIG. 9) remainsin a selected EDO mode until powered down or until another WCBRprogramming cycle is executed to change the mode. This type of switchingmay be employed where a user desires to use burst EDO mode for one ormore applications and pipelined EDO mode for one or more otherapplications. Moreover, an additional external pin may be employed forproviding /OE signal 118 to memory 100 (shown in FIG. 9).

In fixed access-based switching, burst address counter 149 (shown inFIG. 9) may be employed for read operations, and external addressing maybe employed for write operations. In other words, burst EDO mode may beused for read operations, and pipelined EDO mode may be used for writeoperations. In such a case, /WE signal 117 may be applied to modecircuitry 138 (shown in FIG. 11) such that when /WE signal 117 is logiclow, memory 100 is in pipelined EDO mode, and when /WE signal 117 islogic high, memory 100 is in burst EDO mode. This implementationrequires no redefinition of control signals.

Other types of switching include combinations of the above examples. Byway of example and not limitation, a fixed burst-read/pipelined-writeoperation could be combined with a WCBR programming cycle (like thatdescribed in application-based switching) to allow either fixedaccess-based switching or row-based switching.

Referring now to FIG. 18, there is shown a top elevation view of apinout diagram of an memory (DRAM) 240 in accordance with variousembodiments. DRAM 240 has a standard pinout, except for pin 241 (i.e.,pin number eight). Pin 241 has been changed from a NC (no connect) pin,as shown in FIG. 3, to a P/B control signal 120 (shown in FIG. 9) pinfor selecting between burst EDO and pipelined EDO modes of operation. Asmentioned elsewhere herein, an external control signal for modeselection between burst EDO and pipelined EDO need not be present. Insuch a case, logic internal to DRAM 240 is employed for selectingbetween two modes, and thus the pinout of such a DRAM would be the sameas that shown in FIG. 3.

Referring to FIG. 19, there is shown a block diagram of a memory module(SIMM) 250 in accordance with various embodiments. SIMM 250 is similarto that shown FIG. 6, except that P/B control signal 120 is applied to apin on each DRAM 242 through 245, inclusive. DRAMs 242 through 245 aresimilar to that of FIG. 17. Of course, if DRAMs 242 through 245 hadinternal logic for mode selection, no additional providing of P/B signal120 (shown in FIG. 9) would be necessary. In which case, SIMM 250 may belike that of FIG. 6.

Referring to FIG. 20, there is shown system 255 in accordance withvarious embodiments. As illustratively shown, microprocessor 251 iscoupled to memory 100, as well as system clock 253. Notably system clock253 is not directly coupled to memory 100, but is coupled throughmicroprocessor 251.

In this Detailed Description, reference is made to specific examples byway of drawings and illustrations. These examples are described insufficient detail to enable those skilled in the art to practice theinventive subject matter, and serve to illustrate how the inventivesubject matter may be applied to various purposes or embodiments. Otherembodiments are included within the inventive subject matter, aslogical, mechanical, electrical, and other changes may be made to theexample embodiments described herein. Features or limitations of variousembodiments described herein do not limit the inventive subject matteras a whole, and any reference to the invention, its elements, operation,and application are not limiting as a whole, but serve only to definethese example embodiments.

Such embodiments of the inventive subject matter may be referred toherein individually or collectively by the term “invention” merely forconvenience and without intending to voluntarily limit the scope of thisapplication to any single invention or inventive concept, if more thanone is in fact disclosed. Thus, although specific embodiments have beenillustrated and described herein, any arrangement calculated to achievethe same purpose may be substituted for the specific embodiments shown.This disclosure is intended to cover any and all adaptations orvariations of various embodiments. Combinations of the aboveembodiments, and other embodiments not specifically described herein,will be apparent to those of skill in the art upon reviewing the abovedescription.

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract that will allow the reader to quicklyascertain the nature of the technical disclosure. It is submitted withthe understanding that it will not be used to interpret or limit thescope or meaning of the claims. In addition, in the foregoing DetailedDescription, it can be seen that various features are grouped togetherin a single embodiment for the purpose of streamlining the disclosure.This method of disclosure is not to be interpreted to require morefeatures than are expressly recited in each claim. Rather, inventivesubject matter may be found in less than all features of a singledisclosed embodiment. Thus the following claims are hereby incorporatedinto the Detailed Description, with each claim standing on its own as aseparate embodiment.

1. A method of specifying burst or pipeline access to a memory,comprising: receiving an external row address; receiving apipeline/burst select signal; selecting an external address path if thepipeline/burst signal indicates a pipeline mode of operation; andselecting an internal address path if the pipeline/burst signalindicates a burst mode of operation.
 2. The method of claim 1, whereinselecting the external address path includes selecting the externaladdress path from a buffer.
 3. The method of claim 1, further including:generating an internal column address after selecting the internal datapath.
 4. The method of claim 1, further including: obtaining a secondexternal column address subsequent to receiving a first external columnaddress during the pipeline mode of operation.
 5. The method of claim 1,further including: generating an internal column address patterned afteran external column address during the burst mode of operation.
 6. Amemory device, including: external address inputs to receive an externalrow address; a pin to receive a pipeline/burst select signal; andcontrol logic to select an external address path if the pipeline/burstsignal indicates a pipeline mode of operation, and to select an internaladdress path if the pipeline/burst signal indicates a burst mode ofoperation.
 7. The memory device of claim 6, further including: selectioncircuitry to couple to the control logic and to select between a readoperation and a write operation.
 8. The memory device of claim 6,comprising an asynchronous memory device.
 9. The memory device of claim6, furthering including: a temporary storage device to couple to theexternal address path and the internal address path.
 10. The memorydevice of claim 9, further including: a decoder to receive the externalrow address from the temporary storage device.
 11. The memory device ofclaim 9, further including: a counter to couple to the temporary storagedevice, and to receive the external row address to generate an internaladdress.
 12. The memory device of claim 6, further including:asynchronous dynamic random access memory cells to couple to the controllogic.
 13. The memory device of claim 6, further including: a columnaddress decoder to couple to the control logic and to receive anexternal column address.
 14. The memory device of claim 6, wherein thepipeline mode of operation comprises a pipeline extended data outoperation.
 15. The memory device of claim 6, wherein the burst mode ofoperation comprises a burst extended data out operation.
 16. The memorydevice of claim 6, wherein the control logic includes: at least onemultiplexed device.
 17. A system comprising: a microprocessor; and amemory having a pipeline/burst signal input to couple to themicroprocessor, the memory operable to select an external address pathif the pipeline/burst signal indicates a pipeline mode of operation, andto select an internal address path if the pipeline/burst signalindicates a burst mode of operation.
 18. The system of claim 17, furtherincluding: a plurality of addressable memory arrays to couple to themicroprocessor.
 19. The system of claim 17, wherein the memory comprisesa dynamic random access memory.
 20. The system of claim 17, wherein thememory comprises an asynchronous memory.